Samsung has announced the launch of two new advanced process nodes, SF2Z (2nm) and SF4U (4nm), showcasing the rapid pace of technological advancement. Lower nm numbers indicate better performance as smaller transistors result in increased efficiency and reduced power consumption.
The new 2nm process node, SF2Z, features a backside power delivery network (BSPDN) that enhances power, performance, and area (PPA) while reducing voltage drop. PPA are critical variables in optimizing semiconductor designs. In contrast, the 4nm node, SF4U, achieves PPA improvements through optical shrink technology, allowing existing die designs to be scaled down without significant architectural changes.
These cutting-edge process nodes are set to enter mass production in 2025 (4nm) and 2027 (2nm), primarily targeting high-performance computing (HPC) and artificial intelligence (AI) chips. With the potential transfer of this technology to smartphone chips, we may witness a new chapter in the Samsung-Apple rivalry as both companies strive to deliver cutting-edge technology and attract more customers.
Nanometer (nm) nodes determine the size of transistors on a chip, with lower numbers resulting in smaller transistors. Smaller transistors are more efficient, leading to better performance and reduced power consumption. Older chips with 10nm transistors are less efficient than drawing with a thick marker, resulting in slower smartphones.
In comparison, current 5nm, 4nm, and 3nm chips fit more transistors than using a fine-tip pen or pencil tip respectively
